(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to prepare semiconductor surfaces for metal silicide formation.
(2) Description of Prior Art
Micro-miniaturization or the ability to fabricate semiconductor devices with sub-micron features has allowed semiconductor device performance to be increased. Decreases in performance degrading junction capacitances has been achieved as a result of the sub-micron features used for semiconductor devices. However in addition to the capacitance decreases resulting with the use of sub-micron device features, device performance has also been enhanced via the use of lower resistance materials. For example word line and source/drain resistances have been reduced via the use of metal silicide regions formed on both the word line and source/drain regions. Formation of metal silicide on these regions is accomplished selectively via a self aligned metal silicide (salicide) procedure in which metal silicide is formed only selectively on exposed conductive regions such as a polysilicon word line structure and semiconductor source/drain regions. To ensure optimum salicide formation the surfaces of these exposed conductive regions have to be hydrophobic or oxide free, usually accomplished via use of a hydrofluoric acid type wet clean procedure. However insulator regions such as shallow trench isolation (STI) regions incorporated with arsenic ions as a result of previously being exposed to an arsenic ion implantation procedure used for source/drain regions for N channel metal oxide semiconductor field effect transistor (MOSFET) devices, can release the incorporated arsenic ions during the hydrofluoric acid, salicide pre-clean procedure. The released arsenic ions, now in the form of arsenic based defects, can deposit on exposed conductive surfaces such as the word line and source/drain surface, thus deleteriously interfering with subsequent salicide formation on these surfaces.
This invention will describe various solutions for removal of arsenic based defects on conductive surfaces prior to salicide formation. The novel process sequences described in the present invention used for solution or elimination of arsenic based defects allow optimum metal silicide regions to be formed on exposed conductive regions. Prior art such as Hamanaka et al in U.S. Pat. No. 6,569,766 B1, as well as Miyasaka in U.S. Pat. No. 6,673,126 B2, describe cleaning procedures used at various stages of a semiconductor fabrication procedures. However none of the above art describe the novel process solutions offered in the present invention which allows an oxide free and arsenic based defect free conductive surface to be achieved prior to the salicide formation procedure.